By Patra, Amit; Pandit, Soumya; Mandal, Chittaranjan
Reliability issues and the restrictions of method expertise can occasionally limit the innovation approach occupied with designing nano-scale analog circuits. The good fortune of nano-scale analog circuit layout calls for repeat experimentation, right research of the equipment physics, method know-how, and sufficient use of the data database. beginning with the fundamentals, Nano-Scale CMOS Analog Circuits: types and CAD options for High-Level layout introduces the fundamental basic techniques for designing analog circuits with optimum performances. This ebook explains the hyperlinks among the physics and know-how of scaled MOS transistors and the layout and simulation of nano-scale analog circuits. It additionally explores the advance of established computer-aided layout (CAD) recommendations for architecture-level and circuit-level layout of analog circuits. Read more...
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Additional info for Nano-scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design
1. The scaling of the static power dissipation with technology node is shown in Fig. 11. The static power dissipation increases with technology scaling. 1. It is observed that for the HP logic, the static power dissipation is several times that of the LSTP logic. With technology scaling, the increase of static power dissipation is a critical challenge to the IC designers. 6 Scaling of Source-Drain Resistance and Saturation Velocity The variation of the parasitic source-drain resistance (Rdsw ) with technology node is shown in Fig.
12) where Av = gm R is the dc gain of the amplifier, assuming that the output resistance of the transistor is very high. The transconductance gm of the MOS transistor is related to the bias current through IDS = gm vOD where vOD is the equivalent effective overdrive voltage . 3. 13) It is thus observed that the power consumption is proportional to the targeted SNR. Therefore, lowering the supply voltage (and hence the full scale output voltage) without reducing vOD increases the power consumption.
For sub-90nm analog IC design, a paradigm shift in the design methodology is required. The conventional CAD technique needs to be complemented with the technology CAD (TCAD) technique for incorporating the enhanced physical effects of MOS transistors, statistical process variabilities and time dependent reliabilities. The objective of this chapter is to present a comprehensive discussion of the fundamental principles of the construction procedure for high-level models and optimization algorithms.