Logical Effort: Designing Fast CMOS Circuits by Ivan Sutherland, Robert F. Sproull, David Harris

By Ivan Sutherland, Robert F. Sproull, David Harris

Designers of high-speed built-in circuits face a bewildering array of decisions and too frequently spend difficult days tweaking gates to fulfill pace pursuits. Logical attempt: Designing speedy CMOS Circuits makes excessive pace layout more uncomplicated and extra methodical, supplying an easy and extensively appropriate procedure for estimating the hold up due to elements akin to topology, capacitance, and gate sizes.

The brainchild of circuit and special effects pioneers Ivan Sutherland and Bob Sproull, ''logical effort'' will switch how you strategy layout demanding situations. This booklet starts off through equipping you with a valid figuring out of the method's crucial techniques and concepts-so you can begin utilizing it instantly. Later chapters discover the speculation and finer issues of the strategy and element its really expert functions. * Explains the tactic and the way to use it in essentially targeted chapters. * Improves circuit layout instinct by way of instructing basic how you can determine the results of topology and gate measurement judgements. * deals effortless how one can decide upon the quickest circuit from between an array of capability circuit designs. * Reduces the time spent on tweaking and simulations-so you could swiftly choose a great layout. * bargains in-depth insurance of specialised components of program for logical attempt: skewed or unbalanced gates, different circuit households (including pseudo-NMOS and domino), vast buildings corresponding to decoders, and irregularly forking circuits. * provides an entire derivation of the method-so you notice how and why it really works.

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1: Delays for computing the AND of eight inputs for two different values of electrical effort. ✟ ✟ ✂ ✕ ✡ is ✆ ✁ , while when three, we find that the path effort when ✆ ✟ ✟ ✆ ✡✍✝ , ✁ ✍ . 3 shows that when ✁ , a one-stage design will be ✟ ✁ ✍ , a three-stage design will be best. Clearly, cases and best, while when best approximate a one-stage design. It is not immediately obvious whether a two-stage or four-stage path is closest to the three-stage design recommended by the table, but usually it is better to err by one stage too many, as happens in this ✟ example where case is the fastest.

Similarly, the second 0 Copyright c 1998, Morgan Kaufmann Publishers, Inc. This material may not be copied or distributed without permission of the publisher. 23 CHAPTER 2. 1: Three circuits for computing the AND of eight inputs. 1. THE AND FUNCTION OF EIGHT INPUTS 25 circuit is (4-NAND, 2-NOR) and the third is (2-NAND, 2-NOR, 2-NAND, inverter). 1. Let us start the analysis by computing the logical effort of each of the three alternatives. In case , the path logical effort is the product of the logical effort of an 8-input NAND gate, which is ✡ ☛ ✄✂✁ , and that of an inverter, which is 1, so ✂ ✟ ✟ ✡ ☛ ✄✂✁ ✡ ✁ ☞ ✁☛✁ .

To be fair, let the true signals drive a load of 20 unit-sized transistors. 3. The inverter strings used to compute true and complementary versions of the input are called forks and are discussed further in Chapter 6. The 2-inverter and 1-inverter legs of the fork must drive the same load, a NAND gate, in the same amount of time. Computing the best sizes for circuits that fork can require iteration. Fortunately, we can make simple approximations that produce good results. Suppose we keep all sizes the same except to choose a size for the extra inverter.

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