By Manuel J. Bellido
Книга Logic-timing Simulation And the Degradation hold up version Logic-timing Simulation And the Degradation hold up ModelКниги Физика Автор: Manuel J. Bellido, Jorge Juan, Manuel Valencia Год издания: 2006 Формат: pdf Издат.:Imperial collage Press Страниц: 267 Размер: 8,7 ISBN: 1860945899 Язык: Английский0 (голосов: zero) Оценка:Logic-timing Simulation And the Degradation hold up version
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1 Zero delay model. I IN- N 2 I OUT OUT 3 Iu Fig. 2 Unitary delay model. the propagation delay from an input gate to the output. It must be emphasized that in this model all the gates of a circuit have the same timing behaviour. Although the results obtained with this model are not yet accurate enough for temporal verification, they allow for detection of some timing phenomena such as glitches (Fig. 3). 2 Assignable delay models The models that allow for sufficient precision in logic simulation are the assignable delay models.
In fact, pure analytic or heuristic models are not used. The equations to be solved in an analytic approach are usually too complex so it is necessary to make simplifications by introducing fit parameters. On the other hand, the search for modelling expressions in heuristic models is much more efficient if there is a previous analysis. 7 show selected works and their characteristics concerning the former criteria. 6 Summary of characteristics for several delay models (continuation). REF. TECH- ABSTRAC.
They manage devices such as BJT, JFET, MOSFET, etc. But the core of this type of simulators are not the models they use, but how they use them. Due to the commercial secrets which prevail over these simulators, there is little information available, we know the way of operation consists of tabulating the behaviour of the devices so that the execution of the program is much faster and more efficient. Although these simulators increase the benefits of the circuit simulator with a small degradation in the behaviour, nevertheless they have two strong drawbacks: They still have restrictions on the size of the circuit being simulated.