Latchup by Steven H. Voldman

By Steven H. Voldman

Curiosity in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) expertise, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.

Clear methodologies that furnish security from latchup, with perception into the physics, expertise and circuit concerns concerned, are in expanding demand.

This e-book describes CMOS and BiCMOS semiconductor expertise and their sensitivity to offer day latchup phenomena, from easy over-voltage and over-current stipulations, unmarried occasion latchup (SEL) and cable discharge occasions (CDE), to latchup domino phenomena. It includes chapters targeting bipolar physics, latchup thought, latchup and defend ring characterization buildings, characterization trying out, product point try platforms, product point checking out and experimental effects. Discussions on cutting-edge semiconductor tactics, layout structure, and circuit point and method point latchup ideas also are integrated, in addition as:

  • latchup semiconductor method recommendations for either CMOS to BiCMOS, resembling shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from unmarried- to triple-well CMOS; 
  • practical latchup layout equipment, computerized and bench-level latchup checking out tools and strategies, latchup concept of logarithm resistance house, generalized alpha  (a) house, beta (b) area, new latchup layout equipment– connecting the theoretical to the sensible research, and;
  • examples of  latchup laptop aided layout (CAD) methodologies, from layout rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that tackle latchup for inner and exterior latchup on an area in addition to international layout level.

Latchup acts as a spouse textual content to the author’s sequence of books on ESD (electrostatic discharge) security, serving as a useful reference for the pro semiconductor chip and system-level ESD engineer. Semiconductor equipment, approach and circuit designers, and caliber, reliability and failure research engineers will locate it informative at the matters that confront sleek CMOS technology.  Practitioners within the automobile and aerospace industries also will locate it valuable. moreover, its educational therapy will attract either senior and graduate scholars with pursuits in semiconductor method, equipment physics, desktop aided layout and layout integration.

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These circuits may be peripheral receivers, off-chip drivers (OCDs) or ESD networks that are not a function of the power sequencing. This will lead to the prevention of forward biasing of junctions that can lead to latchup. Power application issues – power sequencing with sequence-dependent circuitry: It is a design practice to introduce circuits that are dependent on the power-up and power-down sequencing, by adding additional elements to avoid forward biasing. This will lead to the prevention of forward biasing of junctions that can lead to latchup.

Without the current-limiting element, latchup can introduce chip, board or system failure. 14 CMOS LATCHUP Use of off-chip clamping elements: It is a common latchup practice to have off-chip solutions to avoid overshoot and undershoot phenomena from the board. Use of diode clamping elements or off-chip ESD elements can minimize board- or card-level phenomenon that can trigger latchup. Failure analysis – photoemission failure analysis techniques: Photoemission techniques are a latchup design practice to determine the photon emissions associated with avalanche breakdown, recombination and latchup.

In this transition period, solutions to address latchup such as heavily doped buried layers (HDBLs) were proposed, but no evidence of CMOS latchup concerns was evident [91, 92]. 25 mm to 35 nm, mixed signal integration and the growth of the system-on-chip (SOC), the focus on CMOS latchup has shifted again. During this time, some of the focus remained on CMOS scaling issues [92, 93]. Morris quantified the scaling implications of key latchup metrics and process variables for the prediction of future CMOS latchup concerns [92].

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