Hardware-Software Co-Design of Embedded Systems: The POLIS by Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry

By Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki, Bassam Tabbara (auth.)

Embedded structures are informally outlined as a set of programmable elements surrounded by way of ASICs and different commonplace elements, that have interaction consistently with an atmosphere via sensors and actuators. The programmable components contain micro-controllers and electronic sign Processors (DSPs).
Embedded platforms are frequently utilized in life-critical occasions, the place reliability and security are extra vital standards than functionality. at the present time, embedded platforms are designed with an ad hoc technique that's seriously in accordance with previous event with related items and on guide layout. Use of higher-level languages corresponding to C is helping constitution the layout a little, yet with expanding complexity it's not adequate. Formal verification and automated synthesis of implementations are the ultimate how one can warrantly protection.
therefore, the POLIS method that's a co-design surroundings for embedded platforms relies on a proper version of computation.
POLIS used to be initiated in 1988 as a study undertaking on the collage of California at Berkeley and, through the years, grew right into a complete layout technique with a software program approach assisting it.
Hardware-Software Co-Design of Embedded structures: The POLIS Approach is meant to provide a whole evaluate of the POLIS procedure together with its formal and algorithmic elements.
Hardware-Software Co-Design of Embedded structures: The POLIS Approach can be of curiosity to embedded approach designers (automotive electronics, purchaser electronics and telecommunications), micro-controller designers, CAD builders and students.

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Introduction 29 1. The cost of each node is accurately analyzed. This is a relatively wellunderstood problem, since each S-GRAPH node corresponds roughly to a basic block of code, that is a single-input, single-output sequence of C code statements. 3. 2. The interaction between nodes is limited (also known as the "additivity hypothesis" in the literature). ). We are currently exploring ways of modeling interaction between nodes due to caches, multiple functional units, and pipelines, in order to model complex processors more accurately.

By using Channel Units, the communication is effectively separated from the rest of the design and thus can be optimized and reused. SOLAR is an operational model that focuses on efficient implementation and refinement of communication. For our purposes, its definition was too complex to allow us to apply all the verification and synthesis techniques that are discussed in this book. The UNITY model ([8]) is flat and composed of nodes that implement a set of guarded commands. A guarded command is an assignment of a set of expressions to a set of variables, which is enabled (can be executed) whenever a Boolean expression (its "guard") is true.

Hierarchical decomposition is accomplished by clustering states through the use of AND or OR operations. AND clustering models concurrency (it corresponds to the classical FSM product), while OR clustering models sequencing (the FSM can be in only one of several OR states at a time). Transitions in and out of states or hierarchical states can be specified without restriction. The emphasis of this hierarchical composition is on condensing information. Timing is specified by allowing the use of linear inequalities as timing constraints on states at any hierarchical level.

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