FinFETs and Other Multi-Gate Transistors by J.-P. Colinge

By J.-P. Colinge

This e-book explains the physics and houses of multi-gate field-effect transistors (MuGFETs), how they're made and the way circuit designers can use them to enhance the performances of built-in circuits. It covers the emergence of quantum results end result of the lowered measurement of the units and describes the evolution of the MOS transistor from classical constructions to SOI (silicon-on-insulator) after which to MuGFETs.

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2. Natural length in devices with different geometries. Single gate λ1 = ε si t t ε ox si ox Double gate λ2 = si t t 2εox si ox ε ε si Quadruple gate (square channel cross section) λ4 ≅ Surrounding gate (circular channel cross section)  2t 2ε si t si2 ln 1 + ox t si  16 ε ox λο = 4ε ox t si tox   + ε ox t si2  The following observations can be made: the natural length (and hence short-channel effects) can be reduced by decreasing the gate oxide thickness, the silicon film thickness and by using a high-k gate dielectric instead of SiO2.

Hofmann, M. Specht, U. Dorda, R. Kömmling, L. Dreeskornfeld, J. Kretz, M. Städele, W. Rösner and L. Risch: NVM based on FinFET device structures. Solid-State Electronics 49-11, 1799 (2005) Chang Woo Oh, Sung Dae Suk, Yong Kyu Lee, Suk Kang Sung, Jung-Dong Choe, Sung-Young Lee, Dong Uk Choi, Kyoung Hwan Yeo, Min Sang Kim, Sung-Min Kim, Ming Li, Sung Hwan Kim, Eun-Jung Yoon, Dong-Won Kim, Donggun Park, Kinam Kim, Byung-Il Ryu: Damascene Gate FinFET SONOS Memory Implemented on Bulk Silicon Wafer. Technical Digest of IEDM, 893 (2004) Sang Soo Kim, Won-Ju Cho, Chang-Geun Ahn, Kiju Im, Jong-Heon Yang, In-Bok Baek, Seongjae Lee, Koeng Su Lim: Fabrication of fin field-effect transistor silicon nanocrystal floating gate memory using photochemical vapor deposition.

In the Ω-gate device the value of ENG ranges between 3 and 4 depending on the extension of the gate under the fin. 1 The SOI MOSFET: from Single Gate to Multigate 23 Fig. 12. Maximum allowed silicon film thickness and device width vs. gate length to avoid short-channel effects. The natural length can be used to estimate the maximum silicon film thickness and device width that can be used in order to avoid short-channel effects. 12 shows the maximum allowed silicon film thickness (and device width in a triple-gate device with a square cross section) to avoid short-channel effects.

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