By Brandon Noia, Krishnendu Chakrabarty
This publication describes cutting edge suggestions to handle the trying out wishes of 3D stacked built-in circuits (ICs) that make the most of through-silicon-vias (TSVs) as vertical interconnects. The authors determine the foremost demanding situations dealing with 3D IC trying out and current effects that experience emerged from state of the art study during this area. insurance comprises themes starting from die-level wrappers, self-test circuits, and TSV probing to test-architecture layout, attempt scheduling, and optimization. Readers will make the most of an in-depth examine test-technology strategies which are had to make 3D ICs a truth and commercially plausible.
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Additional info for Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
As the number of dies in a stack, the number of expected bad dies per wafer, or the area of the dies on a wafer increase, the expected compound yield will decrease. Even though wafer sorting can help processes with high m, f , and A, W2W stacking may not be appropriate for these processes. This is because yields are generally very low (< 40 %) even with repositories. As such, D2W or D2D stacking methods may be utilized to achieve acceptable yields. 3 Evaluating the Test Cost with Wafer Matching It is important to evaluate the cost of test versus yield for utilizing wafer repositories .
2 provides a mathematical model for estimating yield and cost of utilizing static repositories for wafer matching and demonstrates the yield improvements that wafer matching offers for stacked ICs. 3 expands the discussion of Sect. 2 to running repositories and evaluates the benefits of different matching flows. 4 discusses fault modeling for stacked memories with resistiveopen defects on TSVs that are utilized as bitlines and wordlines between memory dies. Finally, Sect. 5 examines three different stacked memories with varying test, repair, and redundancy strategies and their impact on stack yield and cost.
20 2 Wafer Stacking and 3D Memory Test Testing of 3D memories is not fundamentally different from testing 2D memories. Many concepts, designs, and applications will be familiar. For example, memory built-in self-test (MBIST) is still utilized to locate faulty memory cells, and built-in self-repair (BISR) mechanisms along with built-in redundancy-analysis (BIRA) circuits allow for a certain level of repairability. There are two predominant BISR architectures for 2D designs that can be mapped to 3D integrated memories: • Decoder redirection BISR is an architecture consisting of four parts.