Design and Modeling for 3DICs and Interposers by Madhavan Swaminathan

By Madhavan Swaminathan

3D Integration is being touted because the subsequent semiconductor revolution. This ebook offers a complete assurance at the layout and modeling features of 3D integration, in fairly, concentrate on its electric habit. taking a look from the viewpoint the Silicon through (TSV) and Glass through (TGV) expertise, the e-book introduces 3DICs and Interposers as a expertise, and provides its software in numerical modeling, sign integrity, energy integrity and thermal integrity. The authors underscored the possibility of this know-how in layout trade codecs and tool distribution.

Readership: Graduate scholars, lecturers, researchers in electric and electronics engineering, machine engineering, semiconductors and packaging.

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A very important item that is neglected here is the mechanical reliability but we assume here that since the coefficient of thermal expansion (CTE) of the silicon interposer is better matched to silicon, this provides a better solution than glass interposer for mechanical reliability. Due to the low resistivity (10Ω-cm) of CMOS grade silicon, the insertion loss of signal lines in the silicon interposer can be a problem. This issue can be corrected either by shielding the signal lines from the silicon substrate by introducing a ground plane or by increasing the resistivity of silicon (as done by Xilinx using a 20Ω-cm silicon substrate).

At that time, the only reason why the silicon MCM technology got a non-favorable response was because the input/output (I/O) terminals were along the periphery of the module which restricted the total number of I/Os that could be supported, thereby limiting the power that could be supplied to the ICs. The edge I/Os also increased the parasitics of these connections. With the advent of TSV technology, these issues no longer exist and therefore from an electrical standpoint, the silicon interposer should provide for a superior solution.

As an example consider the wide I/O application for mobile phones for communication between logic and memory, which is beginning to emerge as a Jedec standard. 8Gbps of data rate will be used to communicate between the two ICs using 512 I/Os. 8. 2Gbps, where the energy consumed per word is roughly 512pJ. The faster data rate and lower energy consumed per word are enabled due to larger bandwidth made possible through more I/O connections (512 vs 64) between the dies and the reduced parasitics of the interconnections.

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