By Brandon Noia, Krishnendu Chakrabarty
This publication describes cutting edge suggestions to handle the trying out wishes of 3D stacked built-in circuits (ICs) that make the most of through-silicon-vias (TSVs) as vertical interconnects. The authors determine the foremost demanding situations dealing with 3D IC trying out and current effects that experience emerged from state of the art study during this area. insurance comprises themes starting from die-level wrappers, self-test circuits, and TSV probing to test-architecture layout, attempt scheduling, and optimization. Readers will make the most of an in-depth examine test-technology strategies which are had to make 3D ICs a truth and commercially plausible.