Architecture of High Performance Computers: Volume I by R. N. Ibbett, N. P. Topham (auth.)

By R. N. Ibbett, N. P. Topham (auth.)

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Ce; with the lock-out digit set, access to that page was only permitted if the address had been generated by the drum or tape systems, or as a result of a peripheral transfer. Secondly, it prevented interference between programs co-existing in the core store; whenever the Supervisor caused a change from one program to another, it protected the pages belanging to the suspended program by setting their lack-out digits. ch paging register. The current process number was held in a register within the processor and updated by the operating systems at a process change.

These figures confirmed the Atlas results which inspired the idea of using a Name Store, but the figures for hit-rates were not as good as bad been anticipated. Thus although 96~1 per cent of name accesses found their operands in one or other Name Store, only 86 per cent of name accesses found their operands in the correct Name Store. 44 Architecture of High Performance Computers - Volume I The comparatively high, and largely unforeseen, amount of interaction between the two Name Stores was found tobe due to the procedure calling mechanism used in MU5.

In all, 14 control digits pass between units via the Exchange, making the total width of the OR gate 113 bits, and some additional control signals pass between the Exchange control logic and each of the units. ). This output buffer is required because, at 47 Storage Hierarchies ~~------------------~---<~ ~~~--------------~ Unit etc. etc. Tag Tag etc. itC. 8 Exchange control and data paths the time SO is sent, either the Receiving Unit may not be free, or a higher priority transfer may be in progress, and the Sending Unit therefore has no means of knowing when the transferwill actually occur.

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