By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in response to Moore’s legislation? At this second, there's no effortless resolution seeing that gate scaling is quickly rising as a major roadblock for the evolution of CMOS know-how. Channel engineering in keeping with high-mobility semiconductor fabrics (e.g. strained Si, replacement orientation substrates, Ge or III-V compounds) might aid conquer the hindrances considering that they give functionality enhancement. There are a number of matters although. can we know the way to make advanced engineered substrates (e.g. Germanium-on-Insulator)? that are the simplest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? do we strategy those fabrics briefly channel transistors utilizing flows, toolsets and understand how just like that during Si expertise? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed thus far, what's the state of the art and that are the most demanding situations forward ahead of we come any on the subject of a practicable Ge and III-V MOS technology.
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